The present invention relates generally to a semiconductor device and to a method for the fabrication of such a semiconductor device. The present invention relates more particularly to an extremely thin semiconductor device of high packaging density type which is capable of coping with multipin (high pin count)-ization and to a method for the fabrication of such a low profile semiconductor device.
The recent trend that electronic equipment is toward becoming smaller and smaller in size requires the high packaging density of semiconductor components such as semiconductor devices of resin-encapsulated type, and semiconductor components are now becoming smaller in size and lower in profile. Further, multipin-ization is now advancing even for small size and thin (low profile) semiconductor devices. There have been placed demands for high-density, downsized, and thin semiconductor devices of the resin-encapsulated type.
Referring now to FIG. 15, a lead frame for a conventional semiconductor device will be described below.
FIG. 15 is a plan view showing a conventional lead frame structure. As shown, the conventional lead frame is made up of a frame portion 101, a rectangular die pad portion 102 within the frame portion 101 on which a semiconductor element will be mounted, a suspension lead portion 103 for supporting the die pad portion 102, a beam-like inner lead portion 104 which is electrically connected, when the semiconductor element is mounted on the die pad portion 102, to the mounted semiconductor element by a connection portion such as a metal fine wire, an outer lead portion 105, formed continuously with the inner lead portion 104, for establishing connection with an external terminal, and a tie bar portion 106 which interconnects and fixes together the outer lead portions 105 and which acts as a resin stopper during resin encapsulation.
Although in the lead frame of FIG. 15 only one pattern of the design of FIG. 15 is illustrated, practically a plurality of such patterns are arrayed laterally and vertically in succession.
Referring next to FIG. 16, a conventional semiconductor device will be described. FIG. 16 schematically depicts, in cross section, a semiconductor device of the resin encapsulation type making utilization of the lead frame of FIG. 15.
As shown in FIG. 16, a semiconductor element 107 is mounted on the die pad portion 102 of the lead frame. The semiconductor element 107 and the inner lead portion 104 are electrically connected together by a metal fine wire 108. The outer peripheries of the semiconductor element 107 on the die pad portion 102 and the inner lead portion 104 are encapsulated by an encapsulating resin 109. The outer lead portion 105 is so provided as to project outside a lateral surface of the encapsulating resin 109 with its end portion bent.
In a conventional semiconductor device fabrication method, the semiconductor element 107 is first bonded onto the die pad portion 102 of the lead frame by an adhesive (the die bond step), as shown in FIG. 17. Following the die bond step, the semiconductor element 107 and the tip of the inner lead portion 104 are connected together by the metal fine wire 108 (the wire bonding step). Thereafter, the outer peripheral of the semiconductor element 107 is subjected to encapsulation. In such encapsulation, the region encapsulated by the encapsulating resin 109 is surrounded by the tie bar portion 106 of the lead frame, while the outer lead portion 105 projects outside (the resin encapsulating step). Lastly, the boundary portion of the encapsulating resin 109 is subjected to cutting at the tie bar portion 106, the outer lead portions 105 are separated from each other, the frame portion 101 is removed, and the tip of the outer lead portion 105 is subjected to bending (the tie bar cut/bend step). In the way described above, the resin-encapsulated type semiconductor device of FIG. 16 can be fabricated. A broken line of FIG. 17 indicates the region to be encapsulated by the encapsulating resin 109.
The conventional lead frame configuration, however, suffers some problems when semiconductor elements are highly integralized and multipin-ized. There is the limit of reducing, when forming an inner lead portion (an outer lead portion), its width. Therefore, if the number of inner lead portions (outer lead portions) is increased with a view to coping with multipin-ization, this usually results in increasing the size of the lead frame itself. As a result, the dimensions of the semiconductor device also increase and it is hard to meet the demand for downsized, thin semiconductor devices. On the other hand, if the number of inner lead portions is increased to cope with semiconductor element multipin-ization without making an alteration in lead frame size, this requires that the width of each inner lead portion be reduced. This will produce many problems with processes such as etching used for lead frame formation.
Recently, as a surface-mount type semiconductor device, certain types of semiconductor devices have been developed (for example, Ball Grid Array (BGA)-type semiconductor devices and Land Grid Array (LGA)-type semiconductor devices). In such a type of semiconductor device, a semiconductor element is mounted on a carrier (a wiring board) having on its bottom surface an external electrode, electrical connections are established, and thereafter the top surface of the carrier is subjected to encapsulation. Such a type of semiconductor device is a semiconductor device onto which bottom surface a mother board is mounted. In future, semiconductor devices of the surface-mount type are expected to become a main stream of semiconductor devices. Accordingly, the problem that conventional lead frames and semiconductor devices making use of such conventional lead frames are unable to keep up with the trend toward the surface-mount type, is becoming serious.
In recent years, technologies for small size/thin packages have been proposed which use no die pad for element mounting. In such technologies, a semiconductor chip is reduced in thickness, electrodes are disposed around the chip, and the outer periphery is single-side encapsulated by encapsulating resin. However, such a single-side encapsulated package has the problem that electrodes are not efficiently exposed from the bottom surface of the encapsulating resin. Moreover, since the thickness is reduced, this produces another problem that stress, caused by encapsulating resin present between electrodes, is applied to these electrodes.